Optimal Design of Channel Doping for Fully Depleted SOI MOSFETs

Fully-depleted SOI devices are being considered for low power applications due to their threshold voltage, sub-threshold slope and capacitance advantages over other technologies. However, the threshold voltage of a fully-depleted SOI device is a strong function of the silicon film and sacrificial oxide thicknesses. Thus, to fully realize the advantages of fully-depleted SOI devices in commercial products, the threshold voltage sensitivity to sacrificial oxide and silicon film variations must be minimized. Using one dimensional numerical simulations, the threshold voltage variation for long channel SOI devices is explored over a range of thickness errors related to silicon film and sacrificial oxide. It is found that the threshold voltage variation is minimized when the peak of the implanted profile is near the center of the silicon film. High variations in sacrificial oxide thickness shift the optimal profile towards the buried oxide while high silicon film thickness variations shift it away from the buried oxide. Thesis Supervisor: Dimitri Antoniadis Title: Professor